rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a wideband, high output current, fast settling op amp AD842 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 connection diagrams features ac performance gain bandwidth product: 80 mhz (gain = 2) fast settling: 100 ns to 0.01% for a 10 v step slew rate: 375 v/ m s stable at gains of 2 or greater full power bandwidth: 6.0 mhz for 20 v p-p dc performance input offset voltage: 1 mv max input offset drift: 14 m v/ 8 c input voltage noise: 9 nv/ ? hz typ open-loop gain: 90 v/mv into a 500 v load output current: 100 ma min quiescent supply current: 14 ma max applications line drivers dac and adc buffers video and pulse amplifiers available in plastic dip, hermetic metal can, hermetic cerdip, soic and lcc packages and in chip form mil-std-883b parts available available in tape and reel in accordance with eia-481a standard product description the AD842 is a member of the analog devices family of wide bandwidth operational amplifiers. this family includes, among others, the ad840 which is stable at a gain of 10 or greater and the ad841 which is unity-gain stable. these devices are fabri- cated using analog devices junction isolated complementary bi- polar (cb) process. this process permits a combination of dc precision and wideband ac performance previously unobtainable in a monolithic op amp. in addition to its 80 mhz gain band- width, the AD842 offers extremely fast settling characteristics, typically settling to within 0.01% of final value in less than 100 ns for a 10 volt step. the AD842 also offers a low quiescent current of 13 ma, a high output current drive capability (100 ma minimum), a low input voltage noise of 9 nv ? hz and a low input offset voltage (1 mv maximum). the 375 v/ m s slew rate of the AD842, along with its 80 mhz gain bandwidth, ensures excellent performance in video and pulse amplifier applications. this amplifier is ideally suited for use in high frequency signal conditioning circuits and wide bandwidth active filters. the extremely rapid settling time of the AD842 makes this amplifier the preferred choice for data acquisition applications which require 12-bit accuracy. the plastic dip (n) package and cerdip (q) package lcc (e) package to-8 (h) package soic (r-16) package AD842 is also appropriate for other applications such as high speed dac and adc buffer amplifiers and other wide band- width circuitry. application highlights 1. the high slew rate and fast settling time of the AD842 make it ideal for dac and adc buffers amplifiers, lines drivers and all types of video instrumentation circuitry. 2. the AD842 is a precision amplifier. it offers accuracy to 0.01% or better and wide bandwidth; performance previ- ously available only in hybrids. 3. laser-wafer trimming reduces the input offset voltage of 1 mv max, thus eliminating the need for external offset nulling in many applications. 4. full differential inputs provide outstanding performance in all standard high frequency op amp applications where the circuit gain will be 2 or greater. 5. the AD842 is an enhanced replacement for the ha2542.
AD842Cspecifications model AD842j/jr 1 AD842k AD842s 2 conditions min typ max min typ max min typ max units input offset voltage 3 0.5 1.5 0.3 1.0 0.5 1.5 mv t min Ct max 2.5/3 1.5 3.5 mv offset drift 14 14 14 m v/ c input bias current 4.2 8 3.5 5 4.2 8 m a t min Ct max 10 612 m a input offset current 0.1 0.4 0.05 0.2 0.1 0.4 m a t min Ct max 0.5 0.3 0.6 m a input characteristics differential mode input resistance 100 100 100 k w input capacitance 2.0 2.0 2.0 pf input voltage range common mode 6 10 6 10 6 10 v common-mode rejection v cm = 10 v 86 115 90 115 86 115 db t min Ct max 80 86 80 db input voltage noise f = 1 khz 9 9 9 nv/ ? hz wideband noise 10 hz to 10 mhz 28 28 28 m v rms open-loop gain v o = 10 v r load 3 500 w 40/30 90 50 90 40 90 v/mv t min Ct max 20/15 25 20 v/mv output characteristics voltage r load 3 500 w 6 10 6 10 6 10 v current v out = 10 v 100 100 100 ma open loop 5 5 5 w frequency response gain bandwidth product v out = 90 mv 80 80 80 mhz full power bandwidth 4 v o = 20 v p-p r load 3 500 w 4.7 6 4.7 6 4.7 6 mhz rise time 5 a vcl = C2 10 10 10 ns overshoot 5 a vcl = C2 20 20 20 % slew rate 5 a vcl = C2 300 375 300 375 300 375 v/ m s settling time 5 10 v step to 0.1% 80 80 80 ns to 0.01% 100 100 100 ns differential gain f = 4.4 mhz 0.015 0.015 0.015 % differential phase f = 4.4 mhz 0.035 0.035 0.035 degree power supply rated performance 15 15 15 v operating range 6 5 6 18 6 5 6 18 6 5 6 18 v quiescent current 13/14 14/16 13 14 13 14 ma t min Ct max 16/19.5 16 19 ma power supply rejection ratio v s = 5 v to 18 v 86 100 90 105 86 100 db t min Ct max 80 86 80 db temperature range rated performance 6 0 +75 0 +75 C55 +125 c package options plastic (n-14) AD842jn AD842kn cerdip (q-14) AD842jq AD842kq AD842sq, AD842sq/883b soic (r-16) AD842jr-16 tape and reel AD842jr-16-reel AD842jr-16-reel7 to-8 (h-12a) AD842jh AD842kh AD842sh lcc (e-20a) AD842se/883b chips AD842jchips AD842schips notes 1 AD842jr specifications differ from those of the AD842jn, jq and jh due to the thermal characteristics of the soic package. 2 standard military drawing available 5962-8964201xx 2a C (se/883b); xa C (sh/883b); ca C (sq/883b). 3 input offset voltage specifications are guaranteed after 5 minutes at t a = +25 c. 4 full power bandwidth = slew rate/2 p v peak . 5 refer to figures 22 and 23. 6 s grade t min Ct max specifications are tested with automatic test equipment at t a = C55 c and t a = +125 c. all min and max specifications are guaranteed. specifications shown in boldface are tested on all production units. specifications subject to change without notice. rev. d C2C (@ +25 8 c and 6 15 v dc, unless otherwise noted)
AD842 rev. d C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 w cerdip (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 w to-8 (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 w soic (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 w lcc (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 6 v storage temperature range q, h, e . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +175 c lead temperature range (soldering 60 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 maximum internal power dissipation is specified so that t j does not exceed +150 c at an ambient temperature of +25 c. thermal characteristics: q jc q ja q sa plastic package 30 c/w 100 c/w cerdip package 30 c/w 110 c/w 38 c/w to-8 package 30 c/w 100 c/w 27 c/w 16-pin soic package 30 c/w 100 c/w 20-pin lcc package 35 c/w 150 c/w recommended heat sink: aavid engineering? #602b metalization photograph contact factory for latest dimensions. dimensions shown in inches and (mm).
figure 1. input common-mode range vs. supply voltage figure 4. quiescent current vs. supply voltage AD842Ctypical characteristics rev. d C4C (at +25 8 c and v s = 6 15 v, unless otherwise noted) figure 2. output voltage swing vs. supply voltage figure 3. output voltage swing vs. load resistance figure 5. input bias current vs. temperature figure 6. output impedance vs. frequency figure 8. short-circuit current limit vs. temperature figure 9. gain bandwidth product vs. temperature figure 7. quiescent current vs. temperature
AD842 rev. d C5C figure 10. open-loop gain and phase margin phase vs. frequency figure 13. common-mode rejection vs. frequency figure 16. harmonic distortion vs. frequency figure 15. output swing and error vs. settling time figure 18. slew rate vs. temperature figure 17. input voltage vs. frequency figure 14. large signal frequency response figure 11. open-loop gain vs. supply voltage figure 12. power supply rejection vs. frequency
AD842 rev. d C6C figure 19b. inverter large signal pulse response figure 20b. noninverting large signal pulse response figure 19c. inverter small signal pulse response figure 20c. noninverting signal pulse response figure 19a. inverting amplifier configuration (dip pinout) figure 20a. noninverting amplifier configuration (dip pinout) offset nulling the input offset voltage of the AD842 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in figure 21 can be used. AD842 settling time figures 22 and 24 show the settling performance of the AD842 in the test circuit shown in figure 23. settling time is defined as: the interval of time from the application of an ideal step function input until the closed-loop amplifier output has entered and remains within a specified error band. this definition encompasses the major components which com- prise settling time. they include (1) propagation delay through the amplifier; (2) slewing time to approach the final output value; (3) the time of recovery from the overload associated with slewing and (4) linear settling to within the specified error band. expressed in these terms, the measurement of settling time is obviously a challenge and needs to be done accurately to assure the user that the amplifier is worth consideration for the application. figure 21. offset nulling (dip pinout) figure 22. AD842 0.01% settling time
AD842 rev. d C7C figure 23. settling time test circuit figure 23 shows how measurement of the AD842s 0.01% set- tling in 100 ns was accomplished by amplifying the error signal from a false summing junction with a very high-speed propri- etary hybrid error amplifier specially designed to enable testing of small settling errors. the device under test was driving a 300 w load. the input to the error amp is clamped in order to avoid possible problems associated with the overdrive recovery of the oscilloscope input amplifier. the error amp gains the er- ror from the false summing junction by 15, and it contains a gain vernier to fine trim the gain. figure 24 shows the long term stability of the settling charac- teristics of the AD842 output after a 10 v step. there is no evi- dence of settling tails after the initial transient recovery time. the use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of tran- sistor isolation capacitance discharge and thermally induced shifts in circuit operating points. these problems do not occur even under high output current conditions. grounding and bypassing in designing practical circuits with the AD842, the user must re- member that whenever high frequencies are involved, some figure 24. AD842 settling demonstrating no settling tails special precautions are in order. circuits must be built with short interconnect leads. large ground planes should be used whenever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high frequency coupling. sockets should be avoided because the increased interlead capacitance can degrade bandwidth. feedback resistors should be of low enough value to assure that the time constant formed with the circuit capacitances will not limit the amplifier performance. resistor values of less than 5 k w are recommended. if a larger resistor must be used, a small (<10 pf) feedback capacitor connected in parallel with the feed- back resistor, r f , may be used to compensate for these stray ca- pacitances and optimize the dynamic performance of the amplifier in the particular application. power supply leads should be bypassed to ground as close as possible to the amplifier pins. a 2.2 m f capacitor in parallel with a 0.1 m f ceramic disk capacitor is recommended. capacitive load driving ability like all wideband amplifiers, the AD842 is sensitive to capaci- tive loading. the AD842 is designed to drive capacitive loads of up to 20 pf without degradation of its rated performance. ca- pacitive loads of greater than 20 pf will decrease the dynamic performance of the part although instability should not occur unless the load exceeds 100 pf. using a heat sink the AD842 draws less quiescent power than most precision high speed amplifiers and is specified for operation without a heat sink. however, when driving low impedance loads, the cur- rent to the load can be 10 times the quiescent current. this will create a noticeable temperature rise. improved performance can be achieved by using a small heat sink such as the aavid engi- neering #602b. terminated line driver the AD842 is optimized for high speed line driver applications. figure 25 shows the AD842 driving a doubly terminated cable in a gain-of-2 follower configuration. the AD842 maintains a typical slew rate of 375 v/ m s, which means it can drive a 10 v, 6.0 mhz signal or a 3 v, 19.9 mhz signal. the termination resistor, r t , (when equal to the characteristic impedance of the cable) minimizes reflections from the far end of the cable. a back-termination resistor (r bt , also equal to the characteristic impedance of the cable) may be placed between the AD842 output and the cable in order to damp any stray sig- nals caused by a mismatch between r t and the cables charac- teristic impedance. this will result in a cleaner signal. with this circuit, the voltage on the line equals v in because one half of v out is dropped across r bt . the AD842 has 100 ma minimum output current and, there- fore, can drive 5 v into a 50 w cable. the feedback resistors, r 1 and r 2 , must be chosen carefully. large value resistors are desirable in order to limit the amount of current drawn from the amplifier output. but large resistors can cause amplifier instability because the parallel resistance r 1 i r 2 combines with the input capacitance (typically 2C5 pf) to create an additional pole. also, the voltage noise of the AD842
AD842 rev. d C8C is equivalent to a 5 k w resistor, so large resistors can signifi- cantly increase the system noise. resistor values of 1 k w or 2 k w are recommended. if termination is not used, cables appear as capacitive loads and can be decoupled from the AD842 by a resistor in series with the output. figure 25. line driver configuration overdrive recovery figure 26 shows the overdrive recovery capability of the AD842. typical recovery time is 80 ns from negative overdrive and 400 ns from positive overdrive. figure 26. overdrive recovery figure 27. overdrive recovery test circuit outline dimensions dimensions shown in inches and (mm). 14-pin plastic (n) package 14-pin cerdip (q) package 12-lead metal can package (to-8 style) 16-lead soic (r-16) package c1195cC5C9/90 printed in u.s.a.
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